As is well known in the art, most integrated circuits are manufactured on wafers, typically semiconductor wafers, and more typically silicon wafers. Wafers have grown from a mere two inches in diameter to eight inches in diameter and, more recently, to twelve inches in diameter, also known as 300 mm wafers. While some devices manufactured today are manufactured on eight-inch wafers, most new integrated device manufacturing facilities will be designed to manufacture on twelve-inch wafers.
As the area of a circle is related to the square of its diameter, a fifty percent increase in the diameter (as in moving from an eight-inch wafer to a twelve-inch wafer) results in more than double the available surface area for manufacturing devices.
Another trend in integrated circuit device manufacturing relates to packaging technology. With the move toward surface mount technology and so called low profile packages, wafers are being ground to increasingly lesser thicknesses as part of the packaging process.
As wafers become larger in diameter and thinner in thickness, previously unknown or at least unappreciated forces play an increasingly important role. These forces include the compressive or tensile stress applied to the wafer, and to the chips in the wafer, by the thin films that are formed thereon as part of the integrated circuit manufacturing processes.
The combination of a greater number of thin films applying stress to thinner wafers/chips results in significant warpage of the wafer/chip and of the subsequently formed integrated circuits. As is known, the wafers are diced into individual chips that, when packaged, form complete integrated circuit devices.
The warpage has several detrimental effects. One of the detrimental effects is that the warpage of chips or wafers can significantly impact the electrical performance of the devices formed in the chips/wafers. As is known, the stress in the semiconductor layer on which MOS transistors are formed can significantly impact charge carrier mobility. The stress caused by the warpage of chips/wafers can adversely impact the charge carrier mobility. In addition, the warpage of chips/wafers causes cold joints in the packaging processes, and may the reduction in yield.